Power management for a computing device may be controlled by placing components of the computing device in various power states to improve energy efficiency. In some cases, it may be desirable to reduce the power consumption of a component of a computing device. However, this may cause a delay for the handling of workloads by the component. In some prior art, a component may be placed in a low power state and then returned to a higher power state relatively soon thereafter to perform a task. If the component is placed in too low of a power state, it may not be able to return from the power state to service a task within a desired amount of time. However, if the component is not placed in a power state that is low enough, it may consume extra power.
Thus, it may be desirable to determine an appropriate low power state for the component. However, this may be challenging because it is difficult to predict when the component will be returned from the low power state. Consequently, some prior art power management techniques result in the consumption of extra power by not placing a component in a low power state when appropriate to do so. Conversely, some prior art power management techniques result in low component performance by not returning a component from a low power state fast enough to perform a task within a desired amount of time.
The same numbers are used throughout the disclosure and the figures to reference like components and features. Numbers in the 100 series refer to features originally found in FIG. 1; numbers in the 200 series refer to features originally found in FIG. 2; and so on.